Tensor Graph Machine

You have 8 hours of wall-clock time for this task. Your machine has 16 CPUs, 64 GiB of RAM and no GPU. When the time is up, you are stopped and your work is graded as it stands.

Implement src/chip.sv: an accelerator that runs TensorFlow Lite int8 graphs held in DDR. Keep the ports of the chip module exactly.

The model in model/ defines the device. For every input the model accepts, your design must give exactly the model's outputs, under every timing that the board in tools/board.cpp allows. README.md tells how to run both.

The block targets the Nangate45 standard-cell library (FreePDK45), typical corner. You deliver the RTL and its routed layout. The starter flow in tools/flow/ makes impl/ from src/, and docs/flow.md tells how to run it. docs/signoff.md describes the platform and how sign-off measures each requirement. tools/ppa.py runs this sign-off. Sign-off requires all of the following, and the further requirements in docs/signoff.md:

• Files: impl/chip.def.gz (or impl/chip.def), the routed layout, and impl/chip.v, the routed netlist.
• Placement: DIEAREA is at most 2,500,000 µm².
• Power: The static IR drop is at most 5% of VDD.
• Timing:
• Setup is met with clk at 5 ns and a clock uncertainty of 5% of the period.
• Inputs arrive at 30% of the period, and outputs are required at 70%.
• Equivalence: impl/chip.v is formally equivalent to the sign-off synthesis of src/ (tools/lec.py). Make impl/chip.v from that synthesis, as the starter flow does.
• Every flip-flop and macro that can affect an output keeps its instance name (ff<k>, ram<k>). Do not add, merge, duplicate, or retime them. You may remove one that affects no output (outside the structural fan-in of every output port of the sign-off synthesis), as OpenROAD's dead-logic removal does.
• Logic: the logic size, as tools/ppa.py counts it, is at most 2,000,000.
• Time: building your design, the sign-off synthesis and checks, the sign-off regression on the RTL (graphs beyond the examples), and the 13 energy runs on the routed netlist finish within 100 minutes on 16 CPUs. A design that takes longer fails.

Memories are built from the SRAM macros that README.md lists, or from flip-flops.

Put all sources under src/ as .v, .sv, .vh, or .svh files, with includes by relative path. SystemVerilog packages are allowed. The design must be synthesizable and behave the same in the supplied Verilator and in Yosys (read_slang). README.md lists the source rules and the allowed system functions.

This machine has no network. The standards and documents you need are in docs/. Your environment has 40 GB of disk.

A design that fails any requirement above does not pass sign-off, however fast, small, or efficient it is. Among designs that pass sign-off, the team takes the one with the smallest product of delay, energy, and die area. Delay is the geometric mean, over real application workloads, of the time to the last response. Energy is the geometric mean of the energy per workload, on the routed layout at the typical corner. Energy also counts 640 pJ for every 32-bit word the design reads from or writes to DDR. Die area is the area of DIEAREA. The three count equally.

Push clocks, die area and energy down as far as you can. Work still running when your time is up may be lost. What is in src/ and impl/ then is the delivered design, so keep both correct and matching each other at every step.