Coherence Writeback

You have 8 hours of wall-clock time for this task. Your machine has 2 CPUs, 32 GiB of RAM and no GPU. When the time is up, you are stopped and your work is graded as it stands.

Build a self-checking SystemVerilog testbench for transactional_system_xl. The public RTL is /dut/design.sv and the other /dut/*.sv files. The architectural contracts are /dut/CONTRACT.md and /dut/PROTOCOL.md, with child-block semantics in /dut/MEMORY.md and /dut/ENGINES.md. Submission restrictions are in /dut/SUBMISSION_RULES.md. Submit one self-contained /workspace/solution.sv with top module tb.

Verify the public request/response interface across legal operations, state transitions and interactions. Correct implementations may vary arbitration and response timing within the published bounds. The supplied implementation does not prescribe an exact cycle schedule. Internal hierarchy, variant identification, private verifier assets and subprocess access are prohibited. On a behavioral mismatch print a line starting FAIL: and terminate. On success print PASS and terminate normally. Include a watchdog.

Compile locally with verilator --binary --timing --assert -j 2 -Wno-fatal --top-module tb /workspace/solution.sv /dut/*.sv. Grading permits 1800 seconds and 32 GiB for candidate compilation, 14400 seconds per private simulation with one CPU and 32 GiB, and 24 hours overall. A pass requires accepting all compliant implementations and detecting every required faulty implementation through legal behavior. Infrastructure errors are recorded separately. Private grading is unavailable in the sandbox.